Semiconductor (SC) devices and integrated circuits (ICs) often make use of integrated capacitors formed between a conductive electrode separated from the semiconductor by a thin dielectric. These are customarily referred to as a metal-oxide-semiconductor (MOS) capacitor or by the abbreviation MOS CAP. Integrated MOS capacitor 20 is shown in FIG. 1 where P or N semiconductor substrate 21 (e.g., silicon) usually has therein N or P well 22 extending to surface 23 on which is provided dielectric layer 24 (e.g., SiO2) surmounted by conductive electrode 25, e.g., a metal or highly doped semiconductor. Dielectric regions 26, 27 (e.g., SiO2) are typically also provided to facilitate lateral isolation of MOS capacitor 20 from other devices and contacts being integrated on SC substrate 21. Highly doped region 28 of the same conductivity type as N or P well 22 is provided for making a low resistance connection to N or P well 22 and terminals 29-1, 29-2 (collectively 29) are coupled to region 28 and overlying electrode 25 so that voltage Vc can be applied to MOS capacitor 20. Dielectric 24 is often formed from an oxide, e.g., SiO2, but that is not essential. Other dielectric materials can also be used. It is customary to refer to this structure as a metal-oxide-semiconductor (MOS) capacitor and by the abbreviation MOS CAP, even when insulating materials other than oxide are used as the dielectric. This convention is followed herein keeping in mind that the word “oxide” is intended to include dielectrics of any insulating material and not be limited merely to compounds containing oxygen. MOS CAP 20 differs from a conventional MOS transistor in that there are no source and drain regions and no lateral current flow in SC region 22 beneath electrode 25.
Because semiconductor N or P well 22 forms one electrode of MOS CAP 20, the capacitance provided by MOS CAP 20 will in general depend upon the applied voltage Vc. Thus, MOS CAP 20 is said to be “non-linear” in the sense that its capacitance is influenced the applied voltage Vc. This effect is well known in the art. Such non-linearity is often a source of problems in integrated circuit design using MOS CAPs. The voltage dependent capacitance of such structures can make it very difficult to maintain the desired circuit properties as the circuit voltage varies. Such voltage dependent capacitance can be avoided by using only metal electrodes and interlayer dielectrics for the capacitors, that is, by not using a semiconductor as one plate of the capacitor. However, this approach usually results in a more complex manufacturing processes and larger occupied integrated circuit area, resulting in higher manufacturing cost. Various other approaches have been tried in the prior art for reducing the voltage dependence of MOS CAPs, but none have been entirely successful or have required processing steps not normally included in the manufacturing sequence for the other devices in the associated integrated circuit (IC) or have required processing steps that can interfere with other aspects of IC manufacture. Accordingly, there is a need for improved device structures and methods of fabrication of MOS capacitors (MOS CAPs) that can substantially mitigate or eliminate their voltage sensitivity, i.e., reduce their voltage non-linearity, without a significant increase in occupied area and/or manufacturing process complexity, or adverse process interactions.